Status : In Production Documents : Visit Microchip Volume Pricing : $2.56 CPU Speed MIPS : 40 Memory Type : Flash Program Memory KBytes : 32 RAM : 2048 Code-Guard Security : Intermediate EEPROM Data Memory : 0 Temperature Range : -40 to 125 Packages : 28/QFN 28/SOIC 300mil 28/SPDIP I/O Pins : 21 Pin count : 28 System Mgmt Features : PBOR POR WDT Internal Oscillator : 7.37 MHz 512 kHz Hardware RTCC : No Direct Memory Access (DMA) Channel : 0 nanoWatt : NO Fast Wake Fast Ctrl Comparators : Analog Peripherals : 10 x 12-bit @ 500 (ksps) 1-A/D CODEC Interface (I2S, AC97) : NO Digital Communication : 1 -UART 0 -A/E/USART 1 -SPI 1 -I2C CRC : NO Peripheral Pin Select (PPS) Crossbar : Yes USB : CAN : 0 - None LIN : NO IrDA : No Capture/Compare/PWM Peripherals : 0 -CCP 0 -ECCP 2 -Std. PWM 16-bit PWM resolution 4 -Input Capture Timers : 0 x 8-bit 3 x 16-bit 1 x 32-bit Motor Control PWM Channels : SMPS PWM Channels : Quadrature Encoder Interface (QEI) : Parallel Port : GPIO JTAG : Boundary Scan ICSP : Yes

dsPIC33FJ32GP202-I/SP-ND Package: SPDIP In Stock: 157 Price (USD): $4.74 dsPIC33FJ32GP202-I/SO-ND Package: SOIC 300 In Stock: 416 Price (USD): $4.50

Operating Range:
 Up to 40 MIPS operation (@ 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
High-Performance DSC CPU:
 Modified Harvard architecture
 C compiler optimized instruction set
 16-bit wide data path
 24-bit wide instructions
 Linear program memory addressing up to 4M instruction words
 Linear data memory addressing up to 64 Kbytes
 83 base instructions, mostly 1 word/1 cycle
 Sixteen 16-bit General Purpose Registers
 Two 40-bit accumulators with rounding and saturation options
 Flexible and powerful addressing modes:
- Indirect
- Modulo
- Bit-Reversed
 Software stack
 16 x 16 fractional/integer multiply operations
 32/16 and 16/16 divide operations
 Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
 Up to ±16-bit shifts for up to 40-bit data
Interrupt Controller:
 5-cycle latency
 118 interrupt vectors
 Up to 21 available interrupt sources
 Up to 3 external interrupts
 7 programmable priority levels
 4 processor exceptions
On-Chip Flash and SRAM:
 Flash program memory (up to 32 Kbytes)
 Data SRAM (2 Kbytes)
 Boot and General Security for Program Flash
Digital I/O:
 Peripheral Pin Select Functionality
 Up to 35 programmable digital I/O pins
 Wake-up/Interrupt-on-Change for up to 21 pins
 Output pins can drive from 3.0V to 3.6V
 Up to 5V output with open drain configuration
 All digital input pins are 5V tolerant
 4 mA sink on all I/O pins
System Management:
 Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
 Power-up Timer
 Oscillator Start-up Timer/Stabilizer
 Watchdog Timer with its own RC oscillator
 Fail-Safe Clock Monitor
 Reset by multiple sources
Power Management:
 On-chip 2.5V voltage regulator
 Switch between clock sources in real time
 Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare:
 Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- 1 timer runs as Real-Time Clock with external
32.768 kHz oscillator
- Programmable prescaler
 Input Capture (up to 4 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
 Output Compare (up to 2 channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM Mode
Communication Modules:
 4-wire SPI
- Framing supports I/O interface to simple codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and sampling modes
 I2C™
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
 UART
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Analog-to-Digital Converters (ADCs):
 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2 and 4 simultaneous samples (10-bit ADC)
- Up to 10 input channels with auto-scanning
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology:
 Low-power, high-speed Flash technology
 Fully static design
 3.3V (±10%) operating voltage
 Industrial and extended temperature
 Low-power consumption
Packaging:
 28-pin SDIP/SOIC/QFN-S

Comming Soon!

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