C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
Up to 1024 bytes Data EEPROM
Up to 64 Kbytes Linear program memory
addressing
Up to 3936 bytes Linear data memory addressing
Up to 16 MIPS operation
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts
31-level, software accessible hardware stack
8 x 8 single-cycle hardware multiplier
Flexible Oscillator Structure:
Precision 16 MHz internal oscillator block:
- Factory calibrated to ± 1%
- Software selectable frequencies range of
31 kHz to 16 MHz
- 64 MHz performance available using PLL –
no external components required
Four crystal modes up to 64 MHz
Two external clock modes up to 64 MHz
4X Phase Lock Loop (PLL)
Secondary oscillator using Timer1 @ 32 kHz
Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
- Two-Speed Oscillator Start-up
Special Microcontroller Features:
